As integrated circuit feature sizes continue to decrease, challenges associated with fabricating the smaller feature sizes continue to increase. For example, difficulty in delineating smaller mask layout features using standard photolithography techniques is becoming a significant contributor to both yield loss and yield variability. To compensate for inadequacies in photolithography capability at the sub-micron level, efforts have been increased in the area of electronic design automation (EDA), such as reticle enhancement technology (RET) and optical proximity correction (OPC). However, complexities of the physical design topography and its complex interaction with the photolithography process make calibration of the RET/OPC software difficult. In addition to calibration difficulty, RET/OPC software is not currently sophisticated enough to make large scale changes to the physical design as is often necessary to resolve certain complex interactions. Thus, use of present EDA technologies often leads to incomplete corrections of the physical design with corresponding systemic yield loss and yield variability problems. Therefore, a method is needed to improve mask layout and fabrication.